1. Field of the Invention
The present invention relates to an amplifier incorporated in a semiconductor integrated circuit for detecting and amplifying the difference between the currents flowing on a pair of signal lines, such as a data bus amplifier incorporated in a dynamic random-access memory (DRAM) or a sense amplifier incorporated in a static random-access memory (SRAM).
2. Description of the Related Art
The "circuit for detecting and amplifying the difference between the currents flowing on a pair of signal lines" to which the present invention is directed is described, for example, in "IEEE International Solid-State Circuits Conference, p. 208, 1992, by K. Sasaki et al." and "Symposium on VLSI Circuits, p. 71, 1990, by E. Seevinck."
In the circuit described in the former literature, since the current sense amplifier which detects and amplifies a differential current supplies its output directly as a signal to the circuit at the next stage, the potential of the output node of the current sense amplifier must be caused to swing fully to a level substantially equal to the supply voltage.
To reduce the time required for one data output and to thereby increase the operating speed, the load capacitance and resistance involved in data transmission must be reduced, but in practice it is difficult to reduce the load capacitance and resistance. Accordingly, if it is attempted to increase the operating speed, the potential of the output node cannot be made to swing fully within a predetermined time and only swings around a level about one half of the supply voltage.
Furthermore, when outputting data continuously, data output is susceptible to the effect of the immediately preceding data output because the potential of the output node begins to rise or fall when the output node is still at a certain potential level depending on the output of the preceding data. The amplitude of the output node potential thus becomes unstable, and if data transmission is continued in this situation, an erroneous operation may result.
On the other hand, the circuit described in the latter literature has the problem that the operating speed decreases when the supply voltage is as low as about 2 V.
When the supply voltage is 3 V or higher, this problem does not show, but when the supply voltage is 2 V or lower, the operating speed decreases due to the low supply voltage and, at the same time, the effect of threshold voltage variations of MOS transistors becomes pronounced, slowing the operation and resulting in reduced margin for supply voltage and threshold levels.